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Month: March 2018

MAX2769 Evaluation Kit: Clock for GPS Receiver

This post exclusively talks about MAX2769CEVKIT.

I have used the evaluation kit for my GPS Receiver development for about ~2+years. When it came to real-time GPS signal processing, things fell apart during the signal tracking phase. After extensive debugging I realised the clock source on the MAX2769C EVKIT was not good enough to support GPS receivers. GPS receivers require a stable and accurate clock for good signal and a reference clock source running via a wire between the front end and the receiver is just a bad idea. Ideally, you want to have the clock source (or the MAX2769 chip) on the same processing board to minimise the phase noise that could be added from the environment or during transmission.

In the board setup image below, ext_clk is the 16.368 MHz clock source. The clock is fed from the front end into the Zybo. I initially wanted to use the 16.368 MHz clock for all the processing as that was the chosen sampling frequency as well. It did not work out how ever as the FIFO in Zybo (FPGA) refused to accept it as a clock signal.

On further investigating, I noticed the deteriorated clock quality received at the Zybo end.

max2769

GPS Receiver Setup (copyrighted)

The first waveform (external_ports_clk_in1) is the clock received as is at the input pin. A lot of harmonics and phase noise is present making it a useless source of clock. There was a need for clock conditioning (to remove jitter) which is why I used Xilinx’s inbuilt core Clocking Wizard. The output of the wizard core is the second waveform (clk_wiz_0_clk_out1). it certainly looks better but the FIFO would still not accept it as a legitimate source of clock. This is a very small snippet provided so there’s a possibility the harmonics and jitter show up at other intervals. The third waveform (FCLK) is simply a clock signal produced by an onboard clock available on Zybo, which is the best of all the three clock signals.

reference_clock

Clock signal comparison (on Zybo) (copyrighted)

This shows that using a clock source from the front end of MAX2769C is not hte best idea and avoid it if you can. If you used the clock source successfully I would very much be interested in hearing from you!

So why not just use the good quality onboard clock? Here’s the catch… The sampling frequency/reference clock of the front end must match with that of the on board clock. Sampling frequency if set up to be 16.368 MHz. The closest frequency that the onboard clock can produce is 16.392 MHz. This might be reasonable for a lot of applications (works for GPS acquistion too!), but not for GPS tracking unfortunately (needs to be exact! and stable).

As a work around I changed the sampling frequency for MAX2769C to 20 MHz (a round number). But there is no way of confirming if this change was actually implemented on the front end. I’m working on GPS data acquistion and will later process it on my PC-based software GPS receiver to check if the sampling frequency did actually change to 20 MHz.

But another uncertainity with using an onboard clock to reference the arrival of the front end data is the phase difference or the delay between the two signals. I’m not sure how that will work out but its something to test for the future.

 

Data acquisition using AXI DMA (ZC706)

I made the switch from Altera to Xilinx a few years ago but haven’t updated the website much. I hope to write more tutorials like this one hoping it helps others who need it (& hopefully won’t have to struggle as much as I had to).

This tutorial uses DMA in Scatter/Gather (SG) mode and will only be used to collect data from the FPGA/PL and store it in memory where the PS/Zynq processor can access/read it.

Firstly, please follow this tutorial that shows you how to setup the DMA in a loop mode. The PS sends some info to the FIFO via a DMA and then receives the same info back in the PS (via the DMA) which confirms the DMA functions properly.

For my project, I only wanted the DMA to write data to memory so I modified somethings from the tutorial in the link. Below are the steps you need to follow.

  1. Select only Write channel
    Capture1

    DMA settings

    Capture2

    DMA connections

2. View full block design

3. If you looked at the full block design you will see the connections running between the blocks. The only custom IP used is the packetgen_axi_v1. This block collects 1-bit data (from a pin, more on this later) and packs it into 32-bit words and transmits it to the FIFO over the AXI.  It is very easy to write this custom IP but if you can’t email me and I’d be able to help you with it.

4. The din input to the custom IP comes from an external pin on the board which is connected to a RF front end. My project collects data from the front end and saves it in memory where the software can later easily access it.

5. Synthesize, Implement and Generate Bitstream for the project. Export the project and launch SDK. Create an application project with hello world.

6. Copy paste the example code from

C:\Xilinx\SDK\version)\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v(ver)\

examples\xaxidma_example_sg_poll.c

7. Here you need to edit out all the parts of the code which involve Tx…

8. In the CheckData() loop instead of checking every individual value received value, just print it out. Also, my custom IP requires a ‘capture_start’ signal from the processor after which it starts collecting data and storing in memory. That collected data will be outputted by the CheckData() function.

9. I highly recommend understanding xaxidma.h header file and all the functions. It will help you customise your application.

10. Program your device and then run the SDK application and you should be able to see a successful run.

 

My next step is to implement a cyclic BD which will continously collect data for a certain period of time. I will post my progress shortly.

 

If you have any comments or suggestions please feel free to leave them below.

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