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Category: Altera

1.7. Using Altera’s FFT Megacore Function

Diving straight into the topic, Altera’s FFT IP is simple to use. With thorough review of the FFT core manual, implementing it gets easier.

Download Altera’s FFT Megacore Function Manual

For my research I needed an FFT function that could transform a long sequence (32,768 samples). Altera has 4 different types of cores available to suit several applications. I compared them all and made an estimate using Quartus and concluded with this table:


These estimates can be found using the FFT Megacore Function settings – Parameterization.

For my application, I needed 3 FFT cores:
1) To transform input signal
2) To transform reference signal
3) Inverse FFT the prodect of signals in 1 & 2.

However, each FFT core occupies a significant portion of the FPGA memory bits and hence I decided to implement just one FFT and use it 3 times. (FFT core can be used for Inverse FFT as well with modification of control signals)

This is the schematic of the design:


The FIFO (First-In, First-Out) is there so that no samples are lost or corrupted before or after tranformation.

While working with Cyclone V SoC, I relayed the information from ARM to the FPGA, transformed it and sent all the data back to ARM.

FFT in hardware does indeed take a shorter time that its equivalent software implementation.

I will provide more elaborate description and Verilog code in the next few days.
If you do not see it here sooner, you can reach me on my email as well :

1.6. Using Nios II Software Build Tools for Eclipse

Before you move on to the software design, make sure the top level module doesn’t have any errors. Of course you won’t know the logical errors until you get to the software design.

Moving on, you will find the Nios II SBT for Eclipse under Tools in the Quartus window.

Choose the default workspace (which should mostly be your project space). Then, to create a new file, choose “Nios II Application and BSP from template”. This will make Nios refer to the design files you created in Quartus. This is a critical link between not just Quartus and Eclipse, but also your hardware and software design.

As shown in the screenshot above, choose the sopcinfo file from the project folder. The Nios CPU name should show. If you have used multiple cpu’s, you must choose the appropriate one. Name your project and for the project template, choose ‘Hello World’. Since we have a SDRAM in our design, we can afford to use this template. If you are using only on-chip memory, then you must choose ‘Hello World Small’, this will shrink the program size and just enough to fit on the on-chip memory.

Hit ‘Finish’ and it should create a bunch of files in the sub-window in the left. In the hello_world.c file the following program was written:


 * “Hello World” example.


 * This example prints ‘Hello from Nios II’ to the STDOUT stream. It runs on

 * the Nios II ‘standard’, ‘full_featured’, ‘fast’, and ‘low_cost’ example

 * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT

 * device in your system’s hardware.

 * The memory footprint of this hosted application is ~69 kbytes by default

 * using the standard reference design.


 * For a reduced footprint version of this template, and an explanation of how

 * to reduce the memory footprint for a given application, see the

 * “small_hello_world” template.



Note: A lot of the statements here may be redundant, but hey, it works 🙂

Then build the program and wait for a ‘Build Finished’ statement. You may face some issue/errors here. One of them can say ‘Permission denied’  which is also the most common one. In such a case open Nios II SBT via Start->All Programs->altera and make sure to roght click on Eclipse and choose “Run as Administrator”. This should solve the problem.

Past all this, you have to RUN the program!

Choose a New Configuration under Run. Choose the project .elf file if its not selected by default. Also select the Target Connection tab and choose the USB Blaster. Check the Ignore mismatched system ID and Ignore mismatched system timestamp if and only if you encounter a problem later during execution of the file. Usually this doesn’t cause a problem.

Then save the configuration and simply Run. It should start processing and soon you will the output on your LCD screen!


At the time of writing this, I have boxed up my amazing Alter DE2-115 kit and brought in an evenmore interesting platform, Cyclone V SX (SoC). So I will no longer post about Cyclone IV but will post about the latest version of Cyclone series. It also has an ARM core! I’m so excited to be working with it. I will however be pleased to answer an questions about any of these kits!

1.5. Using Quartus Programmer

This part onward is my favourite. Actually doing business with the electronics stuff.

Before we ‘burn’ the design onto our chip, let’s get some of the technicalities out of the way. Setting up USB Blaster is easier than I expected it to be. Plug in the USB into your laptop/PC and wait for the driver to get installed. Chances are that it won’t find the appropriate driver, in which case, you direct it to the driver location. Go to the folder which contains Altera>>Quartus>>drivers>>usb blaster

Note: Do not choose the sub folder x32/x64.

This should install the USB Blaster driver and then you are good to go!

Well, almost.

To open the Programmer window, find it under the Tools tab in the Quartus window.

Most things remain unchanged except for the Hardware Setup. Select USB Blaster as the hardware. The file that is important in this case is the .sof file. Check ‘Program & Configure’ and then hit ‘Start’. Minimise this window once the green bar hits 100%.

That was easy wasn’t it?

You are basically done with the hardware design. Congratulations!

Next Post: #6 Using Quartus Eclipse SBT

1.4. Top Level Module Design with VHDL (Example)

After you have your Qsys design ready, you need to move onto defining your top level module. This is nothing but the hardware description or how I like to visualize it is, connecting the hardware peripherals with the software design (from Qsys).

*For the previous steps refer to older posts.*

I will be using the same example I used in the previous post (#3) that is:

AIM: To display “Hello World” on the LCD display using Nios II processor. 

Before we proceed with coding of the top level design, let us get over with ‘Pin Assignments’. In he Quartus window, go to Assignments -> Import Assignments.

Now, to choose the pin assignment file you need the CD that came with the Altera development board. Browse within the CD and search for a file with extension .csv (usually).

Once you’ve assigned Pins, go back to the Quartus Window and again under Assignments go to Assignment Editor. A new Assignment Editor tab should open. For now, leave it open as we will be referring to this later.

So, firstly, create a new VHDL file. (File>>New>>Design>>VHDL File)

Now, the HDL Example from Qsys must be included here. Then build the rest of your code around this. 

When defining your entity, refer to the pins in the Assignment Editor.

Architecture is the place you define the connections between the software and hardware components. (See Example code below).

Note: Update to the Qsys design. I have now also included SDRAM (see image below). I had to add this as on-chip memory is insufficient for most of the processing (further steps). Make sure you change the Reset Vector Memory & Exception Vector Memory (of the Nios processor) to SDRAM.

VHDL code is as below:

WARNING: The variables in VHDL code here depend on the names assigned in the Qsys design. Please make the changes accordingly. Also, the development board I am using is Cyclone IV EP4CE115F. The pin names may change with boards.

After you write this, an important step before you hit Compile:

Go to Project>> Add/Remove Files in Project

    Browse for  <your_filename>.qip file and add it to the project. (In the project folder, it is usually under         synthesis). For some reason this file is not automatically read during compilation and you may get errors.

Wait for the compilation process to complete, which usually takes a couple of minutes depending on your    project. 

When you see compilation successful, it is ready to transfer the design onto the development board!

Next post: Using Quartus Programmer

1.3. Guide to Qsys Design with Nios Processor (Example)

Before you begin with the designing steps, you are expected to have a detailed system schematic of your project. Since the Altera boards have hardware and software components, your system must be distinctly separated into the two categories.

In this post I will be using a simple example which will make explaining easier.

AIM: To display “Hello World” on the LCD display using Nios II processor.

For the rest of my blog posts I will be using the same example.

Always begin with the Qsys design first. In the Quartus window, go to Tools->Qsys.

Another window pops open which most likely looks like this:

In the Library section, you will find all the components/peripherals/features that you can build with. I will start with the Nios processor found under Embedded Processors. An additional window will open where you coon choose among Nios II/e/f/s. I will choose the Nios II/e version because it is the simplest version and also my system doesn’t require the processor to have specific features. We will come back to this window to select Reset Vector Memory and Exception Vector Memory later. Click Finish and now it will appear in the System Contents. 

You have to add 3 more components if you wish to use the Nios processor. They are Timer, JTAG UART and on-chip memory. All of them can be found in the Library. Add them as it is.

Since we will also be using the LCD, add the component too.

Your System Contents should look like this now (with a long list of errors):

I have renamed some of the components just for convenience.

Next step is to make the connections!

Things to keep in mind when making connections:

1. Make sure you connect the data and instruction master to the on-chip memory slave.

2. Make the IRQ connections.

3. If you get ‘memory overlap’ errors, check the Address Map tab. If there is an address overlap, go to System->Assign Base Addresses. This should solve that problem.

4. In the lcd component, external is not connected to anything. Just click where it says ‘Double click to export’.

4. Finally, go back to the Nios processor component and choose on-chip memory as the Reset Vector Memory and Exception Vector Memory.

Hopefully you now have 0 errors and 0 warnings!

Next is to Generate.

Only changes you make here is while choosing between VHDL/Verilog. I am more comfortable using VHDL so that’s what I select and then click Generate.

Once generated sucessfully, go to the Generate tab again and select ‘HDL Example’. Select the appropriate option i.e. VHDL/Verilog and you will see few lines of code below it, something like this:

Now this is the code that you will use in your top level design. For now, you are done with the Qsys design! Close the Qsys window and go back to the Quartus one.

Next steps in the next post!

1.2. Creating a Quartus Project

Creating a Quartus Project is quite straightforward. All you do is name your project and tell the software which Altera platform you are using. Below are the self explanatory screenshots.

1. Nothing to do here. Click on Next.

 2. Select the project directory and name.

Note: Save the project in a folder close to the root directory, sometimes this does become an issue in the later parts of designing.

3. Click Next. Nothing to add here if you are creating a project from scratch.

4. Choose the device you are using here.

5. Click Finish. Now you can start designing your system!

NEXT STEP: Qsys Design

Check the next blog post for guide on Qsys design.

1.1. Working with Altera/Quartus: Design Steps

For my research project, the platform I’m using is Altera’s Cyclone IV. It’s only been a month since I have started working with it and it has been I must say, quite challenging to get the whole idea of the design process and how the different softwares work with each other. The resources available on Altera’s website is extremely useful and informative. However, it took me a while to understand how one design aspect developed in one tool fits in with another developed in a another tool.

In this post I will try and break down the steps involved in general.

Design Steps to follow:

  1. Qsys Design: Qsys is a tool using which you can add different peripherals (SDRAM, Nios II etc) and interconnect them to design your very own custom system. Once your ‘System Contents’ are complete, go to the ‘Generation’ tab and hit ‘Generate’. This will generate a long list of files which will be used later.
  2. Hardware Design: If you are using any external peripherals like LCD or SDRAM then you would need to define how the different components in your Qsys design will connect to the different pins on the chip. To do this, firstly make sure the ‘Pin Assignments’ file is imported. In the Quartus window, go to Assignments->Import Assignments->Select the Pin Assignments file. (Note:The pin assignments file is available in the CD that comes with Altera board.) When you are defining the entity in the VHDL design make sure you use the exact pin names enlisted in the ‘Pin Assignment’ file. To see the pin description, go to Assignments->Assignment Editor.  Once the entity is defined, when defining the architecture, make sure you include the VHDL code generated from the Qsys design. (In Qsys window, go to HDL example tab and copy paste that code into your top level VHDL design.) Once the design is complete, Compile your project.
  3. Using Quartus Programmer: After compilation of your project, now you need to download this design onto your Altera board. To do this, in the Quartus window, go to Tools->Programmer. In the  The first step would  be to complete the Hardware Setup. Make sure your development board is powered on and connected to your PC via the USB-Blaster. (The mode I used was JTAG as I included JTAG UART in my Qsys design). You could Auto-Detect or choose Add File. When you click on Add File, go to your_project_folder->output_files->project_name.sof .Then you simply hit Start and wait till the Progress reaches 100%.
  4. Software Design using Nios SBT for Eclipse: Once the file is downloaded onto the board it is time to move onto the Eclipse tool that you will find again, under the Tools tab. When you start working with SBT, we need to relate our files built here with the ones built in the Quartus project. The .sopc file does exactly that. Therefore in the SBT window, select File->New->Nios II Application and BSP from Template. In the new window that opens, select the sopc file from your project folder. Enter the project name, Hello World as project template (just to keep things simple) and Finish. It will generate a BSP settings file when you Finish. Post this step you will be back on the main Eclipse window after which you can start writing your program in the hello_world.c file. Try simple printf statements for testing. When you want to Compile this program make sure you compile using the Nios II Application which can be setup in Run Configuration.

That’s it! You are done. These are the general steps involved. Next few posts will explain each step in detail and I will take up a simple example that you can try too.

By the time you complete these simple design steps, you may come across many issues/errors. If you do, please ask in the comments and I will do my best to help out. I’ve had my own share of errors and it took me a while to get rid of many.

If you have any suggestions to make please feel free to do that too 🙂

Good Luck!

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