No shortcuts. Work for it.


FPGA-based software GNSS receiver: Tracking issues (Progress Update 1)

Mini-update (01.10.2018): DATASET2** has 8 sample bits packed in bytes which the MATLAB receiver doesn’t like to deal with – even if you specify the data type as ubit1. Best way forward would be to write a script to separate out the bits and create a new data file. (I wrote a C-based converter to take hex values converts it to bits and stores it as individual samples in an int8 format. That seems to work with the receiver.)

My last post talked about how tracking occured periodically. After extensive debugging I found out that the input GPS signal data stream lost about 3 sample bits everytime I would switch between FIFOs (I have two FIFOs acting like ping-pong buffers). In retrospect it is probably not the way to design input buffer streams. Also the test bench I wrote for testing FIFOs would have never caught the problem/bug (now I know).

My new tracking plots look like this (Figure 1):


Figure 1: Tracking results

As you know ideally all the power should appear in the I arm only. This is not the case according to the results.


Figure 1: DLL and FLL discriminator errors

I implemented a Costas loop according to the design and parameters in Scott Gleason’s software receiver. The hardware accumulators pass the values to the microprocessor/ARM every 5ms for tracking loop corrections. So the update to the tracking loops occurs every 5ms or so. Changing filter constants didn’t help my case at all either.

As a different approach to this, I used a DMA to collect about 256 ms of 1-bit GPS data and processed it with various software receivers.

With Kai Borre’s receiver, it acquires the satellites but can’t track them. (I wonder if it is the data format… I do specifiy the data type to be ‘ubit1’ though.)

I tested with my own software receiver and observed the same results, can acquire but can’t track.

Figure 4 below are the ideal results… and Figure 5 is what happens when I process 1-bit GPS data with the same receiver.


Figure 4: Tracking result using Kai Borre’s software receiver (2-bit GPS signal) (DATASET1*)


Figure 5: Tracking result using Kai Borre’s software receiver (1-bit GPS signal) (DATASET2**)

I’m starting to think it is something to do with the dataset itself!

I found a 1-bit GPS dataset online here (DATASET2**). The two software receivers behave similarly. Acquire but don’t track. I think there’s something I’m definitely missing… related to the format perhaps?

DATASET1* GPSdata-DiscreteComponents-fs38_192-if9_55.bin

DATASET2** see link.

DATASET3 (click to download from Google Drive)

[DATASET3 is a short 256ms long 1-bit GPS L1 dataset where each sample is of the type int8, sampling frequency: 16.368 MHz, IF: 4.092 MHz, satellites present: 1, 5, 11, 12, 17, 30]

DATASET4 (click to download from Google Drive)

[DATASET4 is a 500 ms long 1-bit GPS L1 dataset where each sample is of the type int8, sampling frequency: 16.368 MHz, IF: 4.092 MHz, satellites present: 1, 11, 14, 17, 19, 20, 22, 30]

Note: A big thank you to Michele Bavaro for taking interest and providing some suggestions that indeed helped me move ahead (onto the next problem!).



FPGA-based software GNSS receiver: Tracking issues

This post discusses the results of hardware acquisition and some of the current issues I’ve come during tracking of the acquired GNSS signals.

My focus has been implementation of a real-time software GNSS receiver using an FPGA.

My equipment setup is such that I have a GNSS simulator generating GPS signals which are fed into the RF front end. The digital GPS signals are now input to the FPGA development board and this is where all the processing is done in real-time.

I spent quite some designing the flow of data signals from the simulator to the FPGA platform. Extensive work was done by me to setup the interfaces and the protocols.

I’ve managed to complete the implementation of the acquisition module and have been successfully able to acquire satellites in real-time!

I do have a persistent tracking issue however…

Issue: Tracking occurs only at regular intervals for a short duration

Below are some figures showing tracking results.

  • Figure 1: Represents the correlation strength of the IP accumulator (Inphase-Prompt). Expectations are to have a high correlation strength throughout the tracking duration. High correlation however occurs only at certain intervals.

Figure 1

  • Figure 2: This plot compares all the accumulators (Combination of I & Q with Early, Prompt & Late). You immediately notice how all the peaks for all the accumulators occurs at the same time stamps.

Figure 2

  • Figure 3: Becomes more obvious with this plot that ALL the accumulators have high values at similar time intervals

Figure 3

  • Figure 4: This was an interesting plot! I basically zoomed in on the peaks to see what was going on. I noticed how the power would move from Late, Prompt to Early. Every single time. This was a noticeable trend at all the peaks.

Figure 4

The final figure (4) told me that the PRN in the input GPS signal and the one generated on the board do not align during tracking EXCEPT at those peaks.

I went back to check my PRN generators and they work as expected. So if it is not the local PRN signals then what could it be…

That shifted my attention towards the input GPS signal itself. The sampling frequency I used was 20 MHz but perhaps it is not exactly that number? I say this because according to the set sampling frequency, there are 20,000 samples per millisecond. But clearly the PRN in the input signal is shifting (from Late to Early). So does this mean the sampling frequency (aka number of samples per milliseconds) is shifting too? I’m doubting everything at the moment but if you’ve picked up any leads from the figures please let me know as I struggle on to fix it…

Email: surabhisgp [at] gmail [dot] com

MAX2769 Evaluation Kit: Clock for GPS Receiver

This post exclusively talks about MAX2769CEVKIT.

I have used the evaluation kit for my GPS Receiver development for about ~2+years. When it came to real-time GPS signal processing, things fell apart during the signal tracking phase. After extensive debugging I realised the clock source on the MAX2769C EVKIT was not good enough to support GPS receivers. GPS receivers require a stable and accurate clock for good signal and a reference clock source running via a wire between the front end and the receiver is just a bad idea. Ideally, you want to have the clock source (or the MAX2769 chip) on the same processing board to minimise the phase noise that could be added from the environment or during transmission.

In the board setup image below, ext_clk is the 16.368 MHz clock source. The clock is fed from the front end into the Zybo. I initially wanted to use the 16.368 MHz clock for all the processing as that was the chosen sampling frequency as well. It did not work out how ever as the FIFO in Zybo (FPGA) refused to accept it as a clock signal.

On further investigating, I noticed the deteriorated clock quality received at the Zybo end.


GPS Receiver Setup (copyrighted)

The first waveform (external_ports_clk_in1) is the clock received as is at the input pin. A lot of harmonics and phase noise is present making it a useless source of clock. There was a need for clock conditioning (to remove jitter) which is why I used Xilinx’s inbuilt core Clocking Wizard. The output of the wizard core is the second waveform (clk_wiz_0_clk_out1). it certainly looks better but the FIFO would still not accept it as a legitimate source of clock. This is a very small snippet provided so there’s a possibility the harmonics and jitter show up at other intervals. The third waveform (FCLK) is simply a clock signal produced by an onboard clock available on Zybo, which is the best of all the three clock signals.


Clock signal comparison (on Zybo) (copyrighted)

This shows that using a clock source from the front end of MAX2769C is not the best idea and avoid it if you can. If you used the clock source successfully I would very much be interested in hearing from you!

So why not just use the good quality onboard clock? Here’s the catch… The sampling frequency/reference clock of the front end must match with that of the on board clock. Sampling frequency is set up to be 16.368 MHz. The closest frequency that the onboard clock can produce is 16.392 MHz. This might be reasonable for a lot of applications (works for GPS acquistion too!), but not for GPS tracking unfortunately (needs to be exact! and stable).

As a work around I changed the sampling frequency for MAX2769C to 20 MHz (a round number). But there is no way of confirming if this change was actually implemented on the front end. I’m working on GPS data acquistion and will later process it on my PC-based software GPS receiver to check if the sampling frequency did actually change to 20 MHz.

But another uncertainity with using an onboard clock to reference the arrival of the front end data is the phase difference or the delay between the two signals. I’m not sure how that will work out but its something to test for the future.


Phase Increment Calculator for NCO

This Phase Increment Calculator is built specifically for hardware implementation of a Numerically Controlled Oscillator (NCO).

Specify the desired frequency of the output signal of the NCO, the system (or input) clock frequency and the accumulator bit width, to obtain the accumulator value you should use for the NCO.


f_out = [phase_inc/(2N)] * input_clk

Review code: 2-bit Signal Generator (NCO) in Verilog

1.6. Using Nios II Software Build Tools for Eclipse

Before you move on to the software design, make sure the top level module doesn’t have any errors. Of course you won’t know the logical errors until you get to the software design.

Moving on, you will find the Nios II SBT for Eclipse under Tools in the Quartus window.

Choose the default workspace (which should mostly be your project space). Then, to create a new file, choose “Nios II Application and BSP from template”. This will make Nios refer to the design files you created in Quartus. This is a critical link between not just Quartus and Eclipse, but also your hardware and software design.

As shown in the screenshot above, choose the sopcinfo file from the project folder. The Nios CPU name should show. If you have used multiple cpu’s, you must choose the appropriate one. Name your project and for the project template, choose ‘Hello World’. Since we have a SDRAM in our design, we can afford to use this template. If you are using only on-chip memory, then you must choose ‘Hello World Small’, this will shrink the program size and just enough to fit on the on-chip memory.

Hit ‘Finish’ and it should create a bunch of files in the sub-window in the left. In the hello_world.c file the following program was written:


 * “Hello World” example.


 * This example prints ‘Hello from Nios II’ to the STDOUT stream. It runs on

 * the Nios II ‘standard’, ‘full_featured’, ‘fast’, and ‘low_cost’ example

 * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT

 * device in your system’s hardware.

 * The memory footprint of this hosted application is ~69 kbytes by default

 * using the standard reference design.


 * For a reduced footprint version of this template, and an explanation of how

 * to reduce the memory footprint for a given application, see the

 * “small_hello_world” template.



Note: A lot of the statements here may be redundant, but hey, it works 🙂

Then build the program and wait for a ‘Build Finished’ statement. You may face some issue/errors here. One of them can say ‘Permission denied’  which is also the most common one. In such a case open Nios II SBT via Start->All Programs->altera and make sure to roght click on Eclipse and choose “Run as Administrator”. This should solve the problem.

Past all this, you have to RUN the program!

Choose a New Configuration under Run. Choose the project .elf file if its not selected by default. Also select the Target Connection tab and choose the USB Blaster. Check the Ignore mismatched system ID and Ignore mismatched system timestamp if and only if you encounter a problem later during execution of the file. Usually this doesn’t cause a problem.

Then save the configuration and simply Run. It should start processing and soon you will the output on your LCD screen!


At the time of writing this, I have boxed up my amazing Alter DE2-115 kit and brought in an evenmore interesting platform, Cyclone V SX (SoC). So I will no longer post about Cyclone IV but will post about the latest version of Cyclone series. It also has an ARM core! I’m so excited to be working with it. I will however be pleased to answer an questions about any of these kits!

1.5. Using Quartus Programmer

This part onward is my favourite. Actually doing business with the electronics stuff.

Before we ‘burn’ the design onto our chip, let’s get some of the technicalities out of the way. Setting up USB Blaster is easier than I expected it to be. Plug in the USB into your laptop/PC and wait for the driver to get installed. Chances are that it won’t find the appropriate driver, in which case, you direct it to the driver location. Go to the folder which contains Altera>>Quartus>>drivers>>usb blaster

Note: Do not choose the sub folder x32/x64.

This should install the USB Blaster driver and then you are good to go!

Well, almost.

To open the Programmer window, find it under the Tools tab in the Quartus window.

Most things remain unchanged except for the Hardware Setup. Select USB Blaster as the hardware. The file that is important in this case is the .sof file. Check ‘Program & Configure’ and then hit ‘Start’. Minimise this window once the green bar hits 100%.

That was easy wasn’t it?

You are basically done with the hardware design. Congratulations!

Next Post: #6 Using Quartus Eclipse SBT

1.3. Guide to Qsys Design with Nios Processor (Example)

Before you begin with the designing steps, you are expected to have a detailed system schematic of your project. Since the Altera boards have hardware and software components, your system must be distinctly separated into the two categories.

In this post I will be using a simple example which will make explaining easier.

AIM: To display “Hello World” on the LCD display using Nios II processor.

For the rest of my blog posts I will be using the same example.

Always begin with the Qsys design first. In the Quartus window, go to Tools->Qsys.

Another window pops open which most likely looks like this:

In the Library section, you will find all the components/peripherals/features that you can build with. I will start with the Nios processor found under Embedded Processors. An additional window will open where you coon choose among Nios II/e/f/s. I will choose the Nios II/e version because it is the simplest version and also my system doesn’t require the processor to have specific features. We will come back to this window to select Reset Vector Memory and Exception Vector Memory later. Click Finish and now it will appear in the System Contents. 

You have to add 3 more components if you wish to use the Nios processor. They are Timer, JTAG UART and on-chip memory. All of them can be found in the Library. Add them as it is.

Since we will also be using the LCD, add the component too.

Your System Contents should look like this now (with a long list of errors):

I have renamed some of the components just for convenience.

Next step is to make the connections!

Things to keep in mind when making connections:

1. Make sure you connect the data and instruction master to the on-chip memory slave.

2. Make the IRQ connections.

3. If you get ‘memory overlap’ errors, check the Address Map tab. If there is an address overlap, go to System->Assign Base Addresses. This should solve that problem.

4. In the lcd component, external is not connected to anything. Just click where it says ‘Double click to export’.

4. Finally, go back to the Nios processor component and choose on-chip memory as the Reset Vector Memory and Exception Vector Memory.

Hopefully you now have 0 errors and 0 warnings!

Next is to Generate.

Only changes you make here is while choosing between VHDL/Verilog. I am more comfortable using VHDL so that’s what I select and then click Generate.

Once generated sucessfully, go to the Generate tab again and select ‘HDL Example’. Select the appropriate option i.e. VHDL/Verilog and you will see few lines of code below it, something like this:

Now this is the code that you will use in your top level design. For now, you are done with the Qsys design! Close the Qsys window and go back to the Quartus one.

Next steps in the next post!

1.1. Working with Altera/Quartus: Design Steps

For my research project, the platform I’m using is Altera’s Cyclone IV. It’s only been a month since I have started working with it and it has been I must say, quite challenging to get the whole idea of the design process and how the different softwares work with each other. The resources available on Altera’s website is extremely useful and informative. However, it took me a while to understand how one design aspect developed in one tool fits in with another developed in a another tool.

In this post I will try and break down the steps involved in general.

Design Steps to follow:

  1. Qsys Design: Qsys is a tool using which you can add different peripherals (SDRAM, Nios II etc) and interconnect them to design your very own custom system. Once your ‘System Contents’ are complete, go to the ‘Generation’ tab and hit ‘Generate’. This will generate a long list of files which will be used later.
  2. Hardware Design: If you are using any external peripherals like LCD or SDRAM then you would need to define how the different components in your Qsys design will connect to the different pins on the chip. To do this, firstly make sure the ‘Pin Assignments’ file is imported. In the Quartus window, go to Assignments->Import Assignments->Select the Pin Assignments file. (Note:The pin assignments file is available in the CD that comes with Altera board.) When you are defining the entity in the VHDL design make sure you use the exact pin names enlisted in the ‘Pin Assignment’ file. To see the pin description, go to Assignments->Assignment Editor.  Once the entity is defined, when defining the architecture, make sure you include the VHDL code generated from the Qsys design. (In Qsys window, go to HDL example tab and copy paste that code into your top level VHDL design.) Once the design is complete, Compile your project.
  3. Using Quartus Programmer: After compilation of your project, now you need to download this design onto your Altera board. To do this, in the Quartus window, go to Tools->Programmer. In the  The first step would  be to complete the Hardware Setup. Make sure your development board is powered on and connected to your PC via the USB-Blaster. (The mode I used was JTAG as I included JTAG UART in my Qsys design). You could Auto-Detect or choose Add File. When you click on Add File, go to your_project_folder->output_files->project_name.sof .Then you simply hit Start and wait till the Progress reaches 100%.
  4. Software Design using Nios SBT for Eclipse: Once the file is downloaded onto the board it is time to move onto the Eclipse tool that you will find again, under the Tools tab. When you start working with SBT, we need to relate our files built here with the ones built in the Quartus project. The .sopc file does exactly that. Therefore in the SBT window, select File->New->Nios II Application and BSP from Template. In the new window that opens, select the sopc file from your project folder. Enter the project name, Hello World as project template (just to keep things simple) and Finish. It will generate a BSP settings file when you Finish. Post this step you will be back on the main Eclipse window after which you can start writing your program in the hello_world.c file. Try simple printf statements for testing. When you want to Compile this program make sure you compile using the Nios II Application which can be setup in Run Configuration.

That’s it! You are done. These are the general steps involved. Next few posts will explain each step in detail and I will take up a simple example that you can try too.

By the time you complete these simple design steps, you may come across many issues/errors. If you do, please ask in the comments and I will do my best to help out. I’ve had my own share of errors and it took me a while to get rid of many.

If you have any suggestions to make please feel free to do that too 🙂

Good Luck!

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