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Tag: Qsys

1.4. Top Level Module Design with VHDL (Example)

After you have your Qsys design ready, you need to move onto defining your top level module. This is nothing but the hardware description or how I like to visualize it is, connecting the hardware peripherals with the software design (from Qsys).

*For the previous steps refer to older posts.*

I will be using the same example I used in the previous post (#3) that is:

AIM: To display “Hello World” on the LCD display using Nios II processor. 

Before we proceed with coding of the top level design, let us get over with ‘Pin Assignments’. In he Quartus window, go to Assignments -> Import Assignments.

Now, to choose the pin assignment file you need the CD that came with the Altera development board. Browse within the CD and search for a file with extension .csv (usually).

Once you’ve assigned Pins, go back to the Quartus Window and again under Assignments go to Assignment Editor. A new Assignment Editor tab should open. For now, leave it open as we will be referring to this later.

So, firstly, create a new VHDL file. (File>>New>>Design>>VHDL File)

Now, the HDL Example from Qsys must be included here. Then build the rest of your code around this. 

When defining your entity, refer to the pins in the Assignment Editor.

Architecture is the place you define the connections between the software and hardware components. (See Example code below).

Note: Update to the Qsys design. I have now also included SDRAM (see image below). I had to add this as on-chip memory is insufficient for most of the processing (further steps). Make sure you change the Reset Vector Memory & Exception Vector Memory (of the Nios processor) to SDRAM.

VHDL code is as below:

WARNING: The variables in VHDL code here depend on the names assigned in the Qsys design. Please make the changes accordingly. Also, the development board I am using is Cyclone IV EP4CE115F. The pin names may change with boards.

After you write this, an important step before you hit Compile:

Go to Project>> Add/Remove Files in Project

    Browse for  <your_filename>.qip file and add it to the project. (In the project folder, it is usually under         synthesis). For some reason this file is not automatically read during compilation and you may get errors.

Wait for the compilation process to complete, which usually takes a couple of minutes depending on your    project. 

When you see compilation successful, it is ready to transfer the design onto the development board!

Next post: Using Quartus Programmer

1.3. Guide to Qsys Design with Nios Processor (Example)

Before you begin with the designing steps, you are expected to have a detailed system schematic of your project. Since the Altera boards have hardware and software components, your system must be distinctly separated into the two categories.

In this post I will be using a simple example which will make explaining easier.

AIM: To display “Hello World” on the LCD display using Nios II processor.

For the rest of my blog posts I will be using the same example.

Always begin with the Qsys design first. In the Quartus window, go to Tools->Qsys.

Another window pops open which most likely looks like this:

In the Library section, you will find all the components/peripherals/features that you can build with. I will start with the Nios processor found under Embedded Processors. An additional window will open where you coon choose among Nios II/e/f/s. I will choose the Nios II/e version because it is the simplest version and also my system doesn’t require the processor to have specific features. We will come back to this window to select Reset Vector Memory and Exception Vector Memory later. Click Finish and now it will appear in the System Contents. 

You have to add 3 more components if you wish to use the Nios processor. They are Timer, JTAG UART and on-chip memory. All of them can be found in the Library. Add them as it is.

Since we will also be using the LCD, add the component too.

Your System Contents should look like this now (with a long list of errors):

I have renamed some of the components just for convenience.

Next step is to make the connections!

Things to keep in mind when making connections:

1. Make sure you connect the data and instruction master to the on-chip memory slave.

2. Make the IRQ connections.

3. If you get ‘memory overlap’ errors, check the Address Map tab. If there is an address overlap, go to System->Assign Base Addresses. This should solve that problem.

4. In the lcd component, external is not connected to anything. Just click where it says ‘Double click to export’.

4. Finally, go back to the Nios processor component and choose on-chip memory as the Reset Vector Memory and Exception Vector Memory.

Hopefully you now have 0 errors and 0 warnings!

Next is to Generate.

Only changes you make here is while choosing between VHDL/Verilog. I am more comfortable using VHDL so that’s what I select and then click Generate.

Once generated sucessfully, go to the Generate tab again and select ‘HDL Example’. Select the appropriate option i.e. VHDL/Verilog and you will see few lines of code below it, something like this:

Now this is the code that you will use in your top level design. For now, you are done with the Qsys design! Close the Qsys window and go back to the Quartus one.

Next steps in the next post!

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