Diving straight into the topic, Altera’s FFT IP is simple to use. With thorough review of the FFT core manual, implementing it gets easier.
Download Altera’s FFT Megacore Function Manual
For my research I needed an FFT function that could transform a long sequence (32,768 samples). Altera has 4 different types of cores available to suit several applications. I compared them all and made an estimate using Quartus and concluded with this table:
These estimates can be found using the FFT Megacore Function settings – Parameterization.
For my application, I needed 3 FFT cores:
1) To transform input signal
2) To transform reference signal
3) Inverse FFT the prodect of signals in 1 & 2.
However, each FFT core occupies a significant portion of the FPGA memory bits and hence I decided to implement just one FFT and use it 3 times. (FFT core can be used for Inverse FFT as well with modification of control signals)
This is the schematic of the design:
The FIFO (First-In, First-Out) is there so that no samples are lost or corrupted before or after tranformation.
While working with Cyclone V SoC, I relayed the information from ARM to the FPGA, transformed it and sent all the data back to ARM.
FFT in hardware does indeed take a shorter time that its equivalent software implementation.
I will provide more elaborate description and Verilog code in the next few days.
If you do not see it here sooner, you can reach me on my email as well : firstname.lastname@example.org